Développement d’un modèle compact de la jonction tunnel magnétique de première génération et son intégration dans la réalisation d’architectures logiques reprogrammables hybrides magnétique-cmos
Virgile JAVERLIAC
DRFMC/SPINTEC
Mardi 28/11/2006, 14h00
Bât. A, Salle de conférences, 3ème étage, CNRS

Whereas in standard cmos logic the circuit functionality is fixed, in hardware (re)programmable logic circuits it is possible to (re)adapt the functionality to the circuit environment. In this thesis, we study highly reconfigurable circuits which combine cmos and nano-magnetic mram¬-like technologies. Mram having recently demonstrated its potential in terms of speed, endurance and non-volatility, we transfer the concept to fpga circuits. The simulation of such cmos-magnetic hybrid architectures requires at first the development of a spice-like model of the magnetic tunnel junction, which is the building block of the mram cell. This model is further implemented into a standard microelectronics cad flow. Finally, an fpga architecture combining speed and non volatility is proposed and thoroughfully modeled.

Contact : Jerome PLANES

 

Retour en haut