Nanowire transistors in the sub10 nm range are subject to process variability. A main cause is the surface roughness of the nanowire. A single dopant centered in the channel can also modify the room temperature electrical characteristics of the transistor. Both the surface roughness and a centered donor produce confinement potential where a single electron can be trapped and gate manipulated. At the moment these effects are stochastic and very well characterized at low temperature. To quantitatively access these facts and select the best samples to be cooled down the full characteristics should be recorded as function of various parameters, including the substrate voltage. These time consuming experiments- performed over thousands of samples on 300mm wafers done at CEA-LETI-MINATEC - are now possible thanks to a new semi-automatic probe station at INAC-SPSMS. The home-made software interface permits to map the samples and sort out charts with all the important parameters. This tool will be extensively used within the ZeroPOVA DSM-DRT transverse project which concerns the ultimate variability and consumption of small transistors.
Last update : 02/24 2015 (1091)