Apr 22, 2015
Compact modeling and use of Magnetic Tunnel Junctions written by Spin Orbit Torque for non-volatile filp-flops targeting high-speed and low-energy applications

One solution to meet the new microelectronics and very advanced processes issues is to use Magnetic Tunnel Junctions (MTJ), adding mainly the non-volatility to the integrated circuits. This enables to improve the performance, especially in terms of power consumption and new functionalities.

Memory cells, the so-called flip-flops, are widely used in synchronous integrated circuits. The aim of using non-volatile flip-flops is huge: first of all it permits to improve the application reliability since the data can be stored in a permanent manner, even in case of power failure. Second of all, it enables to drastically reduce the power consumption since the power supply can be completely switched off during the sleeping phases of the circuit, which can be more 95% of the time in some cases, such as mobile applications.

 

 

 

 

 

 

 

 

Figure1: SOT-MTJ simulation using the compact model

 

 

 

 

 

 

 

 

 

 

Figure 2: New non-volatile flip-flop architecture based on SOT-MTJ

 

In this work, we developed the first compact model for MTJ written by Spin Orbit Torque (SOT), in Verilog-A language, similarly to what is commonly done for transistors for instance. Design and simulate integrated circuits that use such MTJs is thus possible, for both MRAM memory or logic applications. This model integrates all the physic equations and allows to accurately describe the SOT-MTJ behavior, in terms of magnetization dynamics and resistance variations (Figure 1). Using this model, we have been able to design new non-volatile flip-flops based SOT-MTJ (Figure 2), which have 3 terminals, as fast and their volatile counterparts, and low power consumption. Simulations results showed an increased reliability of such flip-flop architecture, being on the same time 4 times faster and 20 times less power consuming than their Spin Transfer Torque counterparts (STT). A demonstrator embedding several flip-flop-based simple blocks and an SOT-MRAM memory is presently under fabrication.

The main perspective of this work is to integrate these flip-flops to much more complex integrated circuits such as non-volatile digital applications and/or microprocessor.

 

The work and results reported were obtained on the framework of the spOt project (grant agreement n°318144) funded by the European Commission under the Seventh Framework Programme.

 

Last update : 05/27 2016 (1106)

 

Retour en haut