Personal web page : http://inac.cea.fr/Pisp/gregory.dipendina/index.html
Laboratory link : http://www.spintec.fr/
Nowadays, there are several methods to design microelectronics circuits adapted to space applications, meeting the radiation hardening constraints, using specific techniques or fabrication processes.
After a 3 year strong and rich experience in the framework of a Ph. D. in collaboration with CNES, LIRMM and CEA/Spintec, from 2014 to 2017, we would like to expand and reinforce this work. We want to propose novel design architectures embedding emerging non volatile technologies, such as spintronics using MRAM (magnetic memories), for harsh environment, especially for space. Several study have already been done or are currently ongoing on MRAM memories. However, we propose here to integrate MTJ (magnetic Tunnel Junctions), basic element of MRAM, into the computational logic. These MTJs can be used in sequential parts such as flip-flop and latches, or into cells such as NAND, NOR, etc. The final aim is to propose an hybrid CMOS/MRAM logic to harden integrated circuits against space environment. This subject addresses computational digital circuits such as microprocessors for instance. Moreover, STT-MRAM (Spin Transfer Torque) which is the most advanced MRAM technology which start to be commercialized will be used for this work.
On the other hand, the SOT-MRAM (Spin Orbit Torque) technology which is the most emerging MRAM one will also be considered in order to provide the most complete study and the most efficient solution. This work is very prospective and will use very advanced CMOS process. The goal is to fabricate a complete demonstrator and to perform functional and radiation tests with the CNES to validate the robustness of such an approach CMOS/MRAM against particle strikes. This Ph. D. would be mainly co-supervised by the Spintronics IC design team at CEA/Spintec Grenoble and supervised by LIRMM - Montpellier.