PhD subjects

Dernière mise à jour : 18-12-2017

2 sujets INAC

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• Electronics and microelectronics - Optoelectronics

 

System-level simulation and exploration flow for non-volatile neuromorphic architectures

SL-DRF-18-0278

Research field : Electronics and microelectronics - Optoelectronics
Location :

Spintronique et technologie des composants (SPINTEC)

Laboratoire Spintec (SPINTEC)

Grenoble

Contact :

François DUHEM

Benoît MIRAMOND

Starting date : 01-10-2018

Contact :

François DUHEM

CEA - DRF/INAC/SPINTEC/SPINTEC

04 38 78 52 98

Thesis supervisor :

Benoît MIRAMOND

Université Nice Sophia Antipolis - LEAT (Laboratoire d'Electronique, Antennes et Télécommunications) UMR CNRS 7248

04.92.94.28.84

Laboratory link : http://www.spintec.fr/

Hardware neural network implementation is a hot topic in research and is now considered as strategic for several international companies. Leading projects in neuromorphic engineering have led to powerful brain-inspired chips such as SyNAPSE, TrueNorth and SpiNNaker. Most of these technologies work well in centralized computing farms but will not fit embedded systems or Internet-of-Things (IoT) requirements, due to their energy consumption. Heterogeneous integration between CMOS and emergent technologies is seen as an opportunity to go past this limitation. In particular, Magnetoresistive Random-Access Memory (MRAM) is considered one of the most promising Non-Volatile Memory (NVM) technology expected to mitigate energy consumption when integrated in computing architectures. However, we still miss a high-level perspective on how NVM actually benefits energy efficiency and how it can be improved any further.

In this context, the aim of the thesis is to enable exploration of NVM-based neuromorphic accelerators by defining a framework for the joint, high-level modelling of digital logic and NVM-based functions. The framework will enable exploration of new architectural choices based on NVM properties to understand how they affect the performance/energy/area trade-off.

The thesis will be supervised by Professor Benoît Miramond (University Côte d’Azur, LEAT, Sophia Antipolis) and co-supervised by François Duhem (CEA/Spintec, Grenoble).

Applicants should have background in RTL development, system architecture, electronics and programming language such as C/C++ (SystemC appreciated).

MRAM-based synchronous integrated circuit design on advanced technology node for space applications

SL-DRF-18-0178

Research field : Electronics and microelectronics - Optoelectronics
Location :

Spintronique et technologie des composants (SPINTEC)

Laboratoire Spintec (SPINTEC)

Grenoble

Contact :

Gregory DI PENDINA

Lionel TORRES

Starting date : 01-10-2018

Contact :

Gregory DI PENDINA

CEA - DSM/INAC/SPINTEC/SPINTEC

0438784746

Thesis supervisor :

Lionel TORRES

Université de Montpellier - LIRMM

04 67 41 85 67

Personal web page : http://inac.cea.fr/Pisp/gregory.dipendina/index.html

Laboratory link : http://www.spintec.fr/

Nowadays, there are several methods to design microelectronics circuits adapted to space applications, meeting the radiation hardening constraints, using specific techniques or fabrication processes. After a

3 year strong and rich experience in the framework of a Ph. D. in collaboration with CNES, LIRMM and CEA/Spintec, from 2014 to 2017, we would like to expand and reinforce this work. We want to propose novel design architectures embedding emerging non volatile technologies, such as spintronics using MRAM (magnetic memories), for harsh environment, especially for space. Several study have already been done or are currently ongoing on MRAM memories. However, we propose here to integrate MTJ (magnetic Tunnel Junctions), basic element of MRAM, into the computational logic. These MTJs can be used in sequential parts such as flip-flop and latches, or into cells such as NAND, NOR, etc. The final aim is to propose an hybrid CMOS/MRAM logic to harden integrated circuits against space environment. This subject addresses computational digital circuits such as microprocessors for instance. Moreover, STT-MRAM (Spin Transfer Torque) which is the most advanced MRAM technology which start to be commercialized will be used for this work.

On the other hand, the SOT-MRAM (Spin Orbit Torque) technology which is the most emerging MRAM one will also be considered in order to provide the most complete study and the most efficient solution. This work is very prospective and will use very advanced CMOS process. The goal is to fabricate a complete demonstrator and to perform functional and radiation tests with the CNES to validate the robustness of such an approach CMOS/MRAM against particle strikes. This Ph. D. would be mainly co-supervised by the Spintronics IC design team at CEA/Spintec Grenoble and supervised by LIRMM - Montpellier.

 

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